For downsizing of power supply circuits such as a switching power supply, it is effective to increase the switching frequency and reduce the size of passive devices such as inductance and capacitance in power supply circuits. However, the increase in the switching frequency leads to increasing switching loss of switching devices such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or the like, and decreasing power supply efficiency of the switching power supply. Accordingly, for downsizing of power supply circuits such as a switching power supply, it is essential to reduce switching loss while increasing the speed of the switching device.
In MOS gate devices such as a MOSFET, an IGBT, or the like used as a switching device, gate capacitance is reduced by shortening the gate length, thereby the speed being able to be increased. However, reducing the gate capacitance to increase the speed causes resonance between the parasitic inductance included in the wiring and the switching device capacitance. Accordingly, high-frequency noise is generated from the MOS gate device at the time of switching.
As an example for solving the above problem, there is a structure having a p−-type layer provided under a gate electrode of a MOS gate device. Such a structure increases the gate-drain capacitance when a high voltage is applied, whereby temporal variation of the drain voltage (dV/dt) is reduced. Accordingly, switching noise is reduced. However, the manufacturing process of forming a p−-type layer under the gate electrode is complicated. Therefore, a lower limit is caused for cost reduction of MOS gate devices.